1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory and a method of operating the same. More specifically, it relates to a nonvolatile semiconductor memory including contactless cells which allows high integration and a method of operating the same.
2. Description of Related Art
As means of reducing the memory cell size of nonvolatile semiconductor memories, a contactless array has been used. This array does not require contact between bit lines and drain diffusion layers, which allows easy cell designing (scaling) and is adequate for mass storage.
For example, there has been proposed a contactless AND cell as shown in FIGS. 15(a) and 15(b) (IEDM 92, pp. 991-993, 1992).
In this cell, a floating gate 24 is formed on a semiconductor substrate 21 through the intervention of a gate insulating film 23 on a channel formed in the semiconductor substrate 21 between high concentration impurity diffusion layers 22. Additionally, a control gate (CG) 26 is formed on the floating gate 24 through the intervention of an insulating film 25. The high concentration impurity diffusion layers 22 function not only as source/drain regions but also as bit lines.
In the above-described cell, reduction of resistance is necessary to use the high impurity diffusion layers 22 as the bit lines. In general, ions such as phosphorus or arsenic as impurities are implanted at high concentration and heat treatment is performed at 750° C. or higher to activate the high concentration impurity diffusion layers 22.
By the heat treatment, however, the impurities are diffused also in a lateral direction, which increases overlap length between the floating gate 24 and the high concentration impurity diffusion layers 22 as shown in FIG. 15(b). As a result, adjustment of the overlap length becomes difficult.
Moreover, if the cell miniaturization is attempted, the overlap length between the floating gate 24 and the high concentration impurity diffusion layer 22 is an unnegligible factor to ensure effective channel length L for preventing a so-called short channel effect. Therefore, in adjusting gate length M, the adjustment of the overlap length between the floating gate and the high concentration impurity diffusion layer 22 plays an important roll for the cell miniaturization.